Introduction
The neurons modeled on the neural processor are simulated in either a "direct" or a "virtual" implementation. In a direct method, each neuron would have a physical processing element (PE) available which could operate simultaneously in parallel with the other neuron PE's active in the system. In a "virtual" implementation, multiple neurons are assigned to individual hardware processing elements (PEs), requiring that the PE's processing be shared across its "virtual" neurons. The performance of the network will be greater under the "direct" approach, but due to the large number of neurons utilized in many network simulations and technology constraints limiting the number of "direct" neuron PEs which can be implemented, many neurocomputer designs utilize the "virtual" neurons concept to simulate more neurons than are available directly.
The basic concept involved in a virtual neurocomputer is to provide some degree of parallelism, if possible, and then to divide the total number of neurons to be implemented in a network among the parallel processing elements available and to use time division multiplexing per physical processing element. This naturally spreads a single time unit out to cover the processing required for the number of virtual neural nodes assigned to a single physical PE. A virtual neural node represents one neuron in the network being simulated. A uni-processor can be used but it must handle all processing for all neural nodes in a sequential manner. Because of this, many virtual neurocomputers use a parallel arrangement of microprocessors. Parallel arrangements for neurocomputing may be reviewed. See Hecht-Nielsen 90; Savely IEEE 87., and Treleaven 89. The structure used usually allows for floating point hardware accelerators to be added for improved performance of each neural node calculation. An efficient communications network between the physical PE's is also required among the parallel processing elements to improve performance. For these virtual neurocomputers to function, there must be local memory for the physical processors containing the network interconnection structure, weight matrix, and virtual PE activation state memory. There must also be an interface to a host computer, which can be as simple as a personal computer depending upon the requirements to initialize the network, supply input patterns or data, and retrieve and analyze the output patterns or data.